THE CRUNCH
Micron has laid out its DRAM and NAND plans for the coming years, and the headline change is a break with its rivals: the company is abandoning 4F² memory cells, the approach Samsung, SK hynix and CXMT are pursuing, because it sees no viable scaling path beyond Micron's current position. Instead, the roadmap leans on wafer bonding, new materials, High-NA EUV lithography and, eventually, 3D DRAM, which stacks memory cells vertically rather than only shrinking them.
The nearest firm date belongs to the 1δ (1-delta) node, now in yield ramp and scheduled for mass production in the second half of 2027. Micron expects it to raise bit density in the mid-20% range over the current 1γ process, its first DRAM node to use EUV lithography. 1δ will be made in the US and underpin next-generation DDR, LPDDR, graphics memory, HBM5 and vertical memory products.
Later planar nodes are less fully specified. The 1ε process will introduce wafer bonding, building different structures on separate wafers and joining them, though Micron has not said which structures or what gains to expect. The ζÅ node will bring High-NA EUV, a more advanced form of the lithography technique that etches finer patterns, but the company has given no production date, and the source notes it will not arrive until at least 2030, years after Samsung and SK hynix, who plan High-NA adoption in 2028. The ηÅ node is still in pathfinding.
In parallel, Micron is developing two generations of 3D DRAM, called 3D1 and 3D2, and says it will introduce the technology only when it is cost- and performance-competitive with planar memory. No architectures, layer counts or density targets have been disclosed. On the product side, Micron also plans to expand custom DRAM and NAND offerings, as AI developers increasingly want memory tuned to their specific processors and workloads. "DRAM is nearing atomic limits at this point," said Scott DeBoer, Micron's president and chief technology and products officer, adding that the company is focused on introducing 3D DRAM "at the optimal time from a cost and performance point of view".
High-NA EUV is still a young technology across the industry: as of September 2026, Intel reported having processed one million wafers on High-NA tools, a leading milestone for the equipment Micron now plans to adopt for memory. That comparison is between logic-wafer processing volume today and Micron's future memory adoption, so it is not directly equivalent, but it does indicate how early Micron's ζÅ timing is.