HBC stacks multiple layers of LPDDR memory vertically, connected by through-silicon vias, with a compute die at the base that handles AI inference processing close to the memory. Qualcomm argues the approach is more energy efficient than traditional HBM, which stacks standard DDR, because LPDDR chips draw less power while offering similar bandwidth and capacity.

The base-die idea echoes what HBM4 already does, where a logic die sits beneath the memory stack to handle data preparation. Qualcomm's twist is to put compute directly under the memory so data travels a few microns rather than a few centimetres, and the company is targeting a 6x increase in bandwidth per watt compared with the current HBM specification.