THE CRUNCH
Intel's EMIB and Foveros packaging technologies have quietly become the backbone of its high-end client and data centre CPUs, and a detailed look at the company's roadmap shows both are set to keep scaling. EMIB, which entered high-volume manufacturing in 2017, embeds tiny silicon bridges into an organic package substrate only where high-density die-to-die connections are needed, avoiding the cost of a full silicon interposer. The approach has grown from a simple way to link adjacent chiplets into a sophisticated technology underpinning multi-kilowatt processors.
The roadmap shows steady refinement. First-layer interconnect bump pitch has shrunk from 55 microns to 45, with reductions to around 36 microns and ultimately 25 microns planned, which packs more connections along a chiplet's edge. The number of bridges per package has climbed from six to more than 38, and supported HBM memory stacks have grown from four to 24.
New variants add capability rather than just density. EMIB-M builds metal-insulator-metal capacitors into the bridge to steady power delivery near compute dies, addressing power integrity in big processors such as Xeon 6 'Granite Rapids'. EMIB-T goes further with through-silicon vias, letting power travel vertically through the bridge, which matters for multi-kilowatt packages and HBM4-class memory.
Intel's stated end goal is system-in-packages spanning 12 reticles, the maximum area a chip manufacturing mask can expose in one go, built with EMIB and Foveros Direct 3D. EMIB-T is slated to enable 12-reticle designs on a 120×180 mm package around 2028. Beyond that, Intel plans to pair finer-pitch EMIB with glass-core substrates, which resist warpage better than organic materials as packages balloon toward a possible 240×240 mm in the 2030s.