THE CRUNCH

IBM and Siemens have announced a research collaboration to advance IBM's nanostack architecture, a transistor design the company unveiled earlier this year. The partnership combines IBM's semiconductor device work with Siemens' strengths in electronic design automation (EDA), the software used to design chips, along with process simulation, lithography optimisation and advanced manufacturing software.

Nanostack is described as the industry's first known three-dimensional, nanosheet-based design, stacking and staggering transistors vertically to fit more of them on a chip. IBM says its current 7 angstrom node packs nearly 100 billion transistors into a space the size of a fingernail. Because the layers are stacked, different material combinations can be used in each layer, letting each transistor be tuned for performance and power efficiency independently of its neighbours.

The claimed payoff is substantial gains in energy efficiency, performance and SRAM scaling. Note that this is a research collaboration rather than a product launch, and the figures come from IBM's own announcement.